1. Field of the Invention
The present invention relates to a fuse circuit which is used to perform basic setting of e.g., chip operations based on data semipermanently stored in a non-volatile memory element, e.g., a laser fuse, an E-(electrically) fuse, an anti-fuse, and more particularly the present invention is applied to a semiconductor integrated circuit in which data is apt to be damaged due to noises in a transfer path of the data.
2. Description of the Related Art
Conventionally, a non-volatile memory element such as a fuse element is provided in a semiconductor integrated circuit in order to store data concerning operations of internal circuits such as an operating speed or an operating voltage, redundancy data used to remedy a defective cell in a memory circuit, a chip ID, security data and others.
For example, a fuse circuit stores such data by using a fuse set consisting of a plurality of fuse elements. If an electrically programmable element such as an E-fuse, an anti-fuse or the like is used as the fuse element, such data can be stored with any timing both before and after an assembling step.
However, if an electrically programmable element such as an E-fuse or an anti-fuse is used as the fuse element in particular, all data may not be correctly programmed in a programming step in some cases. Further, data concerning an operating of internal circuits or redundancy data is transferred from the fuse circuit to an internal circuit which requires such data through a long transfer path. Therefore, data may be damaged due to noises in the transfer path in some cases.
A technique of a patent cited reference 1 (Japanese patent application laid-open No. 2002-133895) is characterized in that the reliability during reading program data is improved by storing the program data in an anti-fuse pair. That is, writing (dielectric breakdown) is executed with respect to any one of the anti-fuse pair in accordance with a value of the program data. In this case, since a difference in resistance value between the anti-fuse pair when reading the program data (“0” or “1”) can be increased, the reliability of data judgment during reading can be improved.
Therefore, for example, when storing the program data by using one fuse element, irregularities in characteristics (damaged state) of the fuse element adversely affect reading. However, the technique of the patent cited reference 1 can ease such an adverse affect by storing the program data in the anti-fuse pair.
However, even if such a structure is adopted, the technique of the patent cited reference 1 cannot avoid garbled data or the like due to noises generated in the above-described transfer path, for example. An error of a data value caused to due to such garbled data naturally cannot be corrected. Furthermore, in the technique of the patent cited reference 1, since one bit of the program data is stored by using the anti-fuse pair, i.e., two fuse elements, a circuit size is increased, which becomes a factor of an increase in a chip area.
Meanwhile, a technique described in a non-patent cited reference 1 (Michael R. Ouellette, Darren L. Anand, and Peter Jakobsen, “Shared Fuse Macro for Multiple Embedded Memory Devices with Redundancy”, IEEE 2001 Custom Integrated Circuits Conference) concerns a DRAM mixed integrated circuit, and is characterized in that a fuse set consisting of fuse elements as PROMs is constituted as a fuse macro and fuse data is transferred from the fuse macro to a DRAM macro by using a shift register.
In such a structure, however, when a transfer path from the fuse macro to the DRAM macro is very long, there is a risk that erroneous data may be transferred due to skew of a transfer signal or damages of data due to coupling noises. Moreover, a use of an asynchronous transfer circuit can be considered in order to reduce affects of such skew of a transfer signal or coupling noises. In such a case, however, a transfer speed of data is lowered.
Usually, data read from the fuse circuit when turning on a power supply is latched in a latch circuit. However, when there is generated a soft error due to an alpha line described in, e.g., a non-patent cited reference 2 (T. C. May and M. H. Woods, IEEE Trans. Electron Devices ED-26, 2 (1979)) or a soft error due to neutrons described in a non-patent cited reference 3 (J. F. Ziegler et al., “Cosmic Ray Soft Error Rates of 16-Mb DRAM Memory Chips”, IEEE J. Solid-State Circuits, vol. 33, No. 2, February 1998) in connection with data latched in the latch circuit, there occurs a problem that unintentional trimming of operation conditions of an internal circuit or an erroneous remedy of a defective cell in a memory circuit is performed due to erroneous data.
In such a manner, when performing the basic setting of chip operations based on data semipermanently stored in a non-volatile memory element such as a fuse element, if the reliability of a non-volatile memory element itself is low or if there is a risk that the data in the non-volatile memory element is changed to erroneous data in the transfer path or the latch circuit, the prior art does not take any specific countermeasure in order to avoid such a problem.
Therefore, when the erroneous data is read from the non-volatile memory element such as a fuse element or when the erroneous data is generated in the transfer path or the latch circuit, it is desired to correctly perform the basic setting of chip operations, a remedy a defective chip, reading a chip ID or security data.